The use of high speed, small capacity cache memory systems is well known. While there are a variety of cache memory systems, several of the better known are termed "write through" caches and "write back" caches. In a write through cache, data is written into main memory at the same time it is written into the cache. Thus, the cache always contains identical data to that stored in main memory and data integrity (coherency) is maintained throughout the system. The problem with write through architecture is that it creates an excessive amount of bus traffic, in that a write to main memory occurs every time there is a write to the write through cache. A positive aspect of this architecture is that it is always known where the most updated data resides, i.e., everywhere.
In an architecture employing a write back cache, the amount of traffic on the bus is significantly reduced. Initially, data is written into the write back cache from main memory and is then used by the central processing unit (CPU) for operations. When the CPU writes the data back into the cache and assuming it has been modified, a "dirty" bit is set to indicate that the data is now unique to that cache and is different from that which resides in main memory. In such a cache, in general, no immediate effort is made to write the revised data into the main memory to maintain data integrity. Obviously then, it is the dirty bit which is critical to the maintenance of data coherence. So long as a write back cache is utilized with only one processor, data management is straight forward. However, when more than one central processor uses the same main memory, data management problems multiply.
In such systems, there is often more than one cache memory present. Each entry position in a cache is provided with a valid/invalid bit. If a CPU sees that another cache is writing to memory and finds that its cache contains an identical data address, it invalidates its own cache entry rather than updating it. Thus, when a CPU accesses its cache at that particular data address, it finds an invalid entry and is redirected to main memory, a time consuming process.
It is therefore an object of this invention to maintain data integrity in a multi-processor/cache environment without requiring excessive accesses to main memory.
It is another object of this invention to enable a number of CPU's to access data via their associated cache memories with each processor knowing that it is always accessing the most updated data.
It is still another object of this invention to provide a multi-processor system employing write back caches wherein main memory accesses are minimized while simultaneously maintaining data integrity throughout the system.
It is a further object of this invention to provide a cache memory system wherein the use of valid/invalid data indicators are avoided.